1. Field of the Invention
The present invention refers to an input stage with switched capacitors for analog-digital converters.
2. Description of the Related Art
Switched capacitor (SC) circuit structures used in analog-digital converters are generally known. The switched capacitor structures used for sampling an analog signal must have a greater sampling rate than the bandwidth of the signal that has to be converted. Said SC structures may be analog input structures of the analog-digital converters.
FIG. 1 shows an input circuit structure for an analog-digital converter. Said structure 90 is a switched capacitor structure comprising a first switch 1 connected on one side to a terminal Io on which the analog input signal Vin is present and on the other side connected to an armature A of capacitor Ci, a switch 2 positioned between the same armature A of the capacitor Ci and a reference voltage Vref1, a switch 3 positioned between the armature B of the capacitor Ci and another reference voltage Vref2, a switch 4 connected to the armature B and to a next stage of the analog-digital converter. The switches 1-4 are controlled by the signals f1 and f2 shown in FIG. 2; more precisely the switches 1 and 3 are controlled by the signal f1 and the switches 2 and 4 are controlled by the signal f2. The dimension of the capacitor Ci, the conductance during the ignition phase of the switches and the sampling period T determine the dynamic impedance of the structure. The rapid transient of the signal that passes through the elements of the structure 90 causes high current peaks, also called spikes, that can cause problems in the different applications in which said structure is used, for example problems of interfacing with devices on different chips. For this reason the driving stage of said circuit structure has to be carefully designed as in the case of high resolution analog-digital converters (more than 16 bit); in fact, in the latter, the design of said driving stage becomes more and more critical as it may worsen the performances of the converter itself.
Several solutions have been made for this aim.
One way for not having current spikes is to add an input buffer 10 to the structure 90 of FIG. 1 which has the aim of loading it, as shown in FIG. 3. The buffer should have a large bandwidth to guarantee a good regulation of the level of the input signal. This buffer represents an expensive solution in terms of area and power consumption and in addition it introduces noise that could worsen the performances of the entire converter.
Another solution consists of using a further switched capacitor structure 100 to reduce the ignition resistance of the structure 90 of FIG. 1, as can be seen in FIG. 4. The structure 100 is suitable for driving the switch 1 of the circuit structure of FIG. 1 that, in FIG. 4, is represented by a MOS transistor M. The structure 100 comprises the switches 101-103 driven by the signal f2, the switches 104 and 105 driven by the signal f1 and a capacitor Cb. The switch 101 is positioned between the first terminal of the capacitor Cb and the analog signal Vin while the switch 104 is positioned between said first terminal of the capacitor Cb and the gate terminal of the MOS transistor M. The switch 102 is positioned between the second terminal of the capacitor Cb and ground while the capacitor 105 is positioned between said second terminal of the capacitor Cb and a voltage Vdd; the switch 103 is positioned between the gate terminal of the transistor M and ground. The closing of the switches 101-103 permits the capacitor Cb to be loaded at the voltage Vin and to unload the intrinsic capacitances of the transistor M linked to the drain terminal. The successive closing of the switches 104 and 105 enables the MOS transistor M to be driven with a voltage between gate terminal and source terminal equal to Vdd since on the gate terminal the voltage Vdd+Vin is present. Said structure 100 guarantees good linearity of the signal in the input structure but the reduction of the ignition resistance causes an increase of the current spikes in input to the structure of FIG. 1.
A further solution is constituted by a capacitive sampling circuit shown in FIG. 5. Said circuit is similar to the circuit of FIG. 3 in which a switch 11 positioned between the input terminal IN of the buffer 10 and the terminal A of the capacitor Ci has been added. The switches 1 and 11 therefore become the first sampling switches of the structure 90; in fact they are controlled by the signals f1a and f1b shown in FIG. 6 that come from the signal f1 and which both contribute to loading the capacitor Ci up to the voltage level Vin. More precisely considering T as the sampling period, the first semi-sampling period T/2 is divided into two more semi-periods T/4; in the first period T/4 the signal f1a is positive and thus the switch 1 is active, while in the second period T/4 the signal f1b is positive and the switch 11 becomes active. With this solution the noise introduced by the buffer does not invalidate the performances of the converter as said buffer is disconnected during the second period T/4.